Despite the tremendous scaling success of poly-crystalline silicon floating gate (FG) non-volatile memory (NVM) arrays that are fabricated using 20 nm (or smaller) semiconductor fabrication technologies, further scaling of planar memory devices becomes extremely difficult. There are several fundamental reasons for this further scale reduction, including cross-talk between closely located cells, and small numbers of electrons in each FG in the programmed state. This scaling limitation makes implementation of multi-level cell (MLC) technologies featuring several levels of the stored charge in the FG extremely complicated. Hence, three-dimensional (3D) stacked memory devices are being developed to allow the continuation of the stand-alone flash memories scaling roadmap. In the field of embedded memories, 3D back-end (B/E) NVM devices are also challenging because this approach allows larger NVM arrays, even in case of CMOS technologies not scaled to the record technology nodes. Enabled by large volume (>1 Gbit) embedded memory modules, the performance of CMOS products is improved and novel applications appear.
Prior art 2D NVM memory cell arrays are usually formed on the top surface of a silicon substrate. The memory cells are located in the wafer plane and addressed by X-Y decoders. The electrons flow is in the mono-crystalline channels of silicon MOS transistors. The electron mobility in mono-crystalline silicon is high, which is reflected in efficient programming and high access speed of the memory cells. Also, the charge storage material (memory stack), where electrons are stored to set the “1” or “0” data value of each memory cell, is easily fabricated by first oxidizing the mono-crystalline silicon surface, and then depositing the silicon nitride (i.e., when forming an Oxide-Nitride-Oxide (ONO) memory stack) or other storage media (e.g., nano-dots). These memory cells are referred to as “front end” memory cells because the charge storage material is formed directly on the silicon substrate, which serves as a channel during read and write operations. There are no critical thermal budget limitations when forming a subsequent top oxide of ONO-type memory stacks. The top oxide can be formed by direct oxidation of the Nitride, or by chemical vapor deposition (CVD), or atomic layer deposition (ALD) techniques followed by densification at high temperatures. No changes are observed in the mono-crystalline silicon when these processes are used.
An obvious approach for further increasing the density of non-volatile memory devices is creating a stacked memory device, i.e., a device in which layers of memory cells are placed on top of each other. A large effort was put into designing of these types of stacked memory devices. Three dimensional back-end non-volatile memories with NVM transistors employing polycrystalline or amorphous silicon layers as bulk materials are described, e.g., in U.S. Pat. No. 8,048,741 “Semiconductor memory device and method of fabricating the same” (Arai, et al, Toshiba, 2011), U.S. Pat. No. 8,048,741 “Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same” (Lai, et al, Macronix, 2011), and U.S. Pat. No. 8,030,700 Nonvolatile memory device, (Sakamoto, Toshiba; 2011). Recent applications published by Toshiba and Macronix describing emerging 3D NVMs include U.S. Pub. App. No. 20100244119 “Nonvolatile semiconductor memory device and method for manufacturing the same” (Fukuzumi et. al., filed 16 Mar. 2010) and U.S. Pub. App. No. 20100226195 “Integrated Circuit self-aligned 3D memory array and manufacturing method” (Hang-Ting Lue, filed Sep. 9, 2010). These applications generally describe approaches that involve forming layers of poly-crystalline (or amorphous) silicon and a dielectric (e.g., SiO2 or Si3N4) that are then etched to define holes or trenches, and then a memory material (e.g., antifuse, ONO or SONOS memory stacks) are disposed on the exposed side edges of the poly-crystalline (or amorphous) silicon and the dielectric.
There are several problems with conventional 3D NVM approaches such as those mentioned above.
First, in each case the memory transistors' bulk, serving as channel material, is poly-crystalline or amorphous silicon. Even if this channel material is recrystallized (thermally, with the help of power lasers, etc.), the mobility of electrons is still much less in poly-crystalline or amorphous silicon than in mono-crystalline silicon. This lower electron mobility results in increased resistance of the Poly NAND string, resulting in relatively large read-access times and limitations in programming (i.e., because larger voltages are required).
Second, it is difficult to make high quality memory stack on poly-crystalline and amorphous silicon. In common SONOS and nano-dot local charge trapping devices, thermal oxide on crystalline silicon is typically used to ensure further high reliability of the memory cells (i.e., minimal threshold voltage (Vt) shifts and high retention of the stored charge). It is difficult to obtain a high quality thermal oxide on poly-crystalline silicon (i.e., when the channels of thin film transistors are formed first, as taught in U.S. Pub. App. No. 20100226195). In cases where the channels are formed last (e.g., as taught in U.S. Pub. App. No. 20100226195), the situation is even worse, because the oxide facing the transistor channel should be deposited by CVD.
Moreover, the use of poly-crystalline and amorphous silicon to form wordlines and bitlines of the memory array produces pronounced program/erase disturbs in large arrays due to high resistances and large capacitive coupling between adjacent wordline and bitline structures.
What is needed is method for generating a 3D NVM memory array that avoids the issues attributed to the conventional approaches set forth above.